I. Field
This disclosure relates to non-volatile memory devices.
II. Description of Related Art
Non-volatile memory (NVM) devices are used in a wide variety of commercial and military electronic devices and equipment, such as e.g. hand-held telephones, radios and digital cameras. An NVM device comprises an insulating barrier, which can include multiple dielectric layers, located between a charge supply region and a charge storage region. The charge storage region can take the form of a floating gate structure or a charge trapping layer. Programming such NVM devices is accomplished by tunneling charge carriers of a first type, typically electrons, (e.g., from the charge supply region) through the insulating barrier towards the charge storage region.
NVM devices that use charge trapping as a charge storage mechanism instead of a floating gate (FG) are becoming more and more prevalent. Such devices store charge, for example, in a charge trapping layer, such as a silicon nitride layer sandwiched between two oxide layers or, as an alternative, using nano-crystals. Such charge trapping NVM devices are becoming more prevalent, in part, because they are believed to have considerable potential for use in future CMOS generations, in particular, for technologies with dimensions of 90 nm and smaller. One difference between charge trapping devices and floating gate devices is that, for charge trapping devices, electrons are trapped in energy minima that are caused by imperfections in the charge trapping layer, e.g. a silicon nitride layer, or, in the case of nano-crystal memories, on nano-crystals embedded in a gate oxide. These energy minima act as localized charge storage sites that are isolated from each other, in which charge is trapped and stored. In the case of electrons, for example, the free electron energy levels associated with such imperfections and/or nanocrystals are below the free electron energy levels of the surrounding material, thereby creating an energy wells such that, at the location of the imperfections and/or nanocrystals, free electrons are trapped in the created energy wells.
One reason for the growing interest in charge trapping devices is that such devices are relatively easy to scale with associated reductions in physical geometries for future semiconductor processing technology generations. For instance, the use of charge trapping devices eliminates FG patterning issues, such as those related to lithography, overlay and topography.
Moreover, charge trapping devices may be programmed and erased using lower voltages than FG devices implemented on the same semiconductor process. The ability to use lower voltages is important, especially in embedded memories, as the market continues to demand devices that use lower operating voltages and have reduced power consumption. A further advantage of charge trapping NVM devices is excellent program/erase endurance. The program/erase endurance of such charge trapping NVM devices is about two orders of magnitude better than what can be achieved with FG devices.
Current charge trapping NVM devices, however, have certain disadvantages. One disadvantage of such charge trapping devices is their limited data retention capability. Data retention is the ability of an NVM device to retain data programmed into individual memory cells. This limited data retention capability is due, in part, to the use of thin dielectrics between the substrate (e.g., charge supply region) and the charge trapping layer. While the use of a thicker, conventional tunnel dielectric, e.g. SiO2, would improve the data retention capability, this improvement would come at the expense of worsened erase saturation for the devices and, consequently, the duration of a program/erase window (increased duration) for current charge trapping NVM devices. Erase saturation is the inability to completely remove or compensate for the charge stored in the charge storage region of a charge trapping NVM device after programming the device. Therefore, alternative approaches for implementing charge trapping NVM devices are desirable.
The foregoing examples of the related art and limitations related therewith are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those of skill in the art upon a reading of the specification and a study of the drawings.